Instruction Set Architecture

ThruVM implements a RISC-V virtual machine that executes smart contract bytecode on the Thru blockchain. The VM is fully compliant with the RISC-V specification and supports multiple standard extensions for comprehensive computational capabilities. Execution on ThruVM is single-threaded and is entirely deterministic. No atomic access to data outside of the virtual machine execution, which implies sequential consistency for all memory operations.

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RISC-V Specification Compliance

ThruVM is fully compliant with the RISC-V Instruction Set Manual, Version 20250508. The implementation adheres to all architectural requirements and behavioral specifications defined in this version.

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Supported Extensions

ThruVM supports the following RISC-V instruction set extensions:

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Instruction Set Architecture Details

The following are a brief description of the base ISA and

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Base ISA (RV64I)

The RV64I base instruction set provides:

• 64-bit integer registers: 32 general-purpose registers (x0-x31) with x0 hardwired to zero
• Load/Store architecture: Memory access only through explicit load and store instructions
• Arithmetic operations: Addition, subtraction, logical operations (AND, OR, XOR)
• Shift operations: Logical and arithmetic left/right shifts
• Comparison operations: Set-less-than for signed and unsigned comparisons
• Branch instructions: Conditional branches based on register comparisons
• Jump instructions: Unconditional jumps with optional link register updates
• System instructions: Environment calls and control/status register access

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Multiplication and Division (M Extension)

The M extension adds support for:

• Integer multiplication: MUL, MULH, MULHSU, MULHU
• Integer division: DIV, DIVU, REM, REMU
• 32-bit variants: MULW, DIVW, DIVUW, REMW, REMUW for RV64

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Compressed Instructions (C Extension)

The C extension provides 16-bit instruction encodings for:

• Common operations: Register-register operations, immediate operations
• Memory access: Compressed load/store instructions
• Control flow: Compressed branch and jump instructions
• Stack operations: Stack pointer manipulation instructions

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Bit Manipulation (B Extension)

The B extension includes instructions for:

• Bit counting: Count leading/trailing zeros (CLZ, CTZ)
• Bit manipulation: Single-bit operations, bit field operations
• Rotation: Left and right rotations (ROL, ROR)
• Permutation: Byte and nibble permutation operations
• Carry-less multiplication: CLMUL, CLMULH, CLMULR

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Cryptographic Hash Functions (Zknh Extension)

The Zknh extension provides acceleration for:

• SHA-256: SHA256SIG0, SHA256SIG1, SHA256SUM0, SHA256SUM1
• SHA-512: SHA512SIG0, SHA512SIG1, SHA512SUM0, SHA512SUM1

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Programmer and Implementer Considerations

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Illegal Instructions

Using instructions that are currently unimplemented will cause the VM to exit with an illegal instruction exception (SIGILL), resulting in transaction revert. If an instruction becomes implemented in future versions, programs using those instruction encodings will automatically adopt the new behavior. To explicitly indicate illegal instructions, use encodings with all bits set to 0 or all bits set to 1.

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Memory Alignment

ThruVM enforces strict alignment requirements:

• Instructions: Must be aligned to 16-bit boundaries
• Data access: Unaligned memory access is not supported and will trigger an exception

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System Calls

For details on the syscall calling convention and available system calls, refer to the Syscalls documentation.

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Register Conventions

ThruVM follows standard RISC-V register conventions: